TSMC is reportedly developing a new advanced chip packaging technology called CoPoS (Chip-on-Panel-on-Structure), according to sources familiar with the matter. The process uses a glass-based temporary carrier and integrates into the final substrate using a three-layer “sandwich” structure.

The new packaging approach is expected to move into mass production by the end of 2028. If successful, it could reduce manufacturing costs while also improving overall chip performance.

TSMC is said to be targeting CoPoS primarily at AI and high-performance computing chips, rather than general consumer processors.

In terms of early adoption, Nvidia’s Feynman AI chip is reportedly set to be the first product to use the CoPoS packaging technology. This would align with the growing demand for more efficient and powerful AI hardware.

If CoPoS delivers on its promises, it could further strengthen TSMC’s position in the semiconductor industry, particularly in advanced packaging. It may also push competitors to develop alternative packaging methods to keep up.

On the demand side, companies like Nvidia are expected to benefit first as AI and HPC workloads continue to scale rapidly.